1. Field of the Invention
This invention relates to a semiconductor memory device having the function of relieving (or overcoming) faults by using redundancy selecting lines when the faults occur in some of a plurality of selecting lines for writing or reading data by selecting a specific memory cell from among a plurality of memory cells, and also to a method for executing this shift redundancy operation.
When large capacity semiconductor memory devices such as the latest dynamic random access memories (DRAMS), static random access memories (SRAMs), flash memories, ferromagnetic random access memories (FRAMs), etc., are massproduced, it is practically difficult to manufacture semiconductor chips (semiconductor integrated circuits) perfectly free from faults in selecting lines, and the like. Because the possibility of the occurrence of faults is particularly high at the initial stage of mass production, the semiconductor chips must be discarded in the worst case and the production yield of the chips is likely to drop. To minimize the drop of the yield, countermeasures for relieving the faults by utilizing redundancy circuit elements such as redundancy selecting lines, that are disposed in advance in the semiconductor chip, must be essentially employed.
On the other hand, high operation speed and low power consumption have been required for the recent large capacity semiconductor memory devices. Therefore, the redundancy system described above that utilizes the redundancy circuit elements must have a high shift redundancy speed and accomplish a high-speed access, and must have low power consumption, and must be able to efficiently relieve (or overcome) the faults on the semiconductor chip.
2. Description of the Related Art
Various systems have been employed as the redundancy system utilizing the redundancy circuit elements in the semiconductor chip, and a shift redundancy system among them has the features such as a high access speed and a small consumed current (consumed power), and is believed to be an effective means for recent large capacity semiconductor memory devices.
Here, the construction of a typical semiconductor memory device according to the prior art, and its operation, will be explained with reference to FIG. 1 of later-appearing “BRIEF DESCRIPTION OF THE is DRAWINGS” in order to have the problems of conventional semiconductor memory devices having the redundancy function more easily understood.
FIG. 1 is a block diagram showing the construction of an ordinary semiconductor memory device having a redundancy function. In the semiconductor memory device such as a DRAM, a row decoder 800 and a column decoder 700 operating on the basis of the address signals supplied from external are provided to a plurality of memory cells 600 arranged in a matrix, as shown in FIG. 1. These row decoder 700 and column decoder 700 are connected to row selecting lines WL and column selecting lines CL, respectively, and are used for writing or reading data by selecting a specific memory cell from among a plurality of memory cells on the basis of the address signals Add (A0 to An) of the decode signal.
In the ordinary redundancy systems, the redundancy operation is executed by replacing the row selecting line or column selecting line (hereinafter referred to merely as the “selecting lines” unless specified otherwise), in which a fault occurs, by redundancy selecting lines for relieving the fault that are prepared in advance.
In practice, a redundancy decision circuit 840 compares the input address with the address of the fault selecting line, that is in advance detected and stored, whenever the address of the address signal Add is inputted, and judges whether or not the input address is in conformity with the address of the fault selecting line (conformity/inconformity). On the other hand, the address of the address signal Add is serially inputted to the row decoder 800 without passing through the redundancy decision circuit 840. When the redundancy decision circuit 840 judges that a certain input address is not coincident with the address of the fault selecting line, the row decoder 800 receives this judgement result and selects the selecting line (row selecting line) corresponding to the input address. When a certain input address is judged as being coincident with the address of the fault selecting line, the row decoder 800 does not select the selecting line corresponding to the input address but selects the redundancy selecting line. In this way, the redundancy decision circuit 840 judges conformity/inconformity between the input address and the fault selecting lines for all the input addresses.
Furthermore, the redundancy decision circuit 740 compares the input address with the address of the fault selecting line that is in advance detected and stored, whenever the address of the address signal Add is inputted, and judges whether or not the input address coincides with the address of the fault selecting line (conformity/inconformity). On the other hand, the address of the address signal Add is serially inputted to the column decoder 700 without passing through the redundancy decision circuit 740. When the redundancy decision circuit 740 judges that a certain input address does not coincide with the address of the fault selecting line, the column decoder 700 receives this judgement result and selects the selecting line (column selecting line) corresponding to this input address. When a certain input address is judged as being coincident with the address of the fault selecting line, the column decoder 700 does not select the selecting line corresponding to the input address but selects the redundancy selecting line. In this way, the redundancy decision circuit 740 judges conformity/inconformity between the input address and the fault selecting line for all the input addresses.
The explanation will be given hereby in further detail on the operation when the fault occurs in the column selecting lines CL (selecting lines s0 to sn and in redundancy selecting line sj0) with reference to FIG. 1. When a redundancy enable (activation) signal JEN outputted from the redundancy decision circuit 740 is at the “L (Low)” level (that is, when the input address and the address of the fault selecting line are not judged as coincident), the column decoder 700 decodes the input address of the address signal Add as usual and selects the object selecting line from among the selecting lines s0 to sn. When the redundancy enable signal JEN outputted from the redundancy decision circuit 740 is at the “H (High)” level (that is, when the input address and the address of the fault selecting line are judged as coincident), on the other hand, the column decoder 700 brings the selecting line, which is to be selected from the input address, into the non-selection state and selects the redundancy selecting line sj0.
On the other hand, the operation will be given in further detail when any fault occurs in the row selecting lines WL with reference to FIG. 1. When the redundancy enable (activation) signal JEN outputted from the redundancy decision circuit 840 is at the “L” level (that is, when the input address and the address of the fault selecting line are not judged as coincident), the row decoder 800 decodes the input address of the address signal Add as usual and selects the object selecting line from among a plurality of selecting lines. When the redundancy enable signal JEN outputted from the redundancy decision circuit 840 is at the “H” level (that is, when the input address and the address of the fault selecting line are judged as coincident), on the other hand, the row decoder 800 brings the selecting line, that is to be selected from the input address, into the non-selection state and selects the redundancy selecting line.
As described above, the address signal Add is serially inputted to the column decoder 700 (or to the row decoder 800) irrelevantly to the redundancy judgement operation of the redundancy decision circuit 740 (or the redundancy decision circuit 840). Therefore, the redundancy enable signal JEN outputted as the judgement result from the redundancy decision circuit 740 (or 840) is inputted to the column decoder 700 (or to the row decoder 800) more belatedly than the timing at which the address signal Add is inputted to the column decoder 700 (or to the row decoder 800: with the proviso that delay circuits 720 and 820 shown in FIG. 1 do not exist). Here, if the path through which the address signal Add is inputted to the column decoder 700 (or to the row decoder 800) is not retarded time-wise, the selecting line that should originally be subjected to redundancy (that is, the selecting line to be brought into the non-selection state) is often selected for a certain period of time. To avoid such a problem, the address signal must be decoded after the redundancy judgement of the redundancy decision circuit 740 (or the redundancy decision circuit 840) is done, by a method that disposes a delay circuit 720 in the path through which the address signal Add is supplied to the column decoder 700 (or disposes a delay circuit 820 in the path through which the address signal Add is supplied to the row decoder 800), or like means. Due to this delay time by the delay circuit, the access time gets prolonged at the time of the data write or read operation, and the high-speed access becomes difficult. Furthermore, the redundancy decision circuit 740 (or the redundancy decision circuit 840) must be operated whenever the address signal Add is inputted, and the consumed current (consumed power) increases, in consequence.
Unlike the system described above which directly replaces the fault selecting line by the redundancy selecting line, the shift redundancy system having the shift redundancy function according to the prior art operates a plurality of switch devices so that the addresses of the selecting lines of the high order (or the low order) can be shifted by one bit to the lower order (or to the higher order) by the fault selecting lines. In such a shift redundancy system, once the connection relationship between the decode signal outputted from the column decoder 700 (or the row decoder 800) and the column selecting line CL (or the row selecting line) is determined by a plurality of switch devices, this relationship remains unaltered. Therefore, it is not necessary to operate the redundancy decision circuit in order to judge conformity/inconformity between the input address and the address of the fault selecting line. As a result, the access speed becomes relatively higher and the consumed current becomes smaller in the semiconductor device using the conventional shift redundancy system.
However, the shift redundancy system according to the prior art can shift decode signal lines by only one bit, that is, by only one selecting line (or in other words, it can execute the shift redundancy operation of only one bit). Therefore, if two or more than two fault selecting lines exist due to short circuit between the selecting lines, etc., this system cannot relieve such fault selecting lines.
For this reason, even when the conventional shift redundancy system is employed, the faults on the semiconductor chip cannot be relieved efficiently, and the production yield of the chips cannot be greatly improved.
In a semiconductor chip equipped with a plurality of cell arrays each including a plurality of memory cells, a redundancy decision circuit, etc, is generally disposed independently so as to correspond to each cell array. Therefore, the degree of freedom of redundancy can be secured for only the total number of selecting lines (the row selecting lines or the column selecting lines) inside one cell array.
Furthermore, when the shift redundancy operation is executed for the column selecting lines disposed for a plurality of row blocks, whether or not the shift redundancy operation is executed for the column selecting lines is determined uniformly for all the row blocks. Therefore, the redundancy operation is not executed for all the row blocks, or the shift redundancy operation is executed for the same column selecting lines of all the row blocks. Consequently, redundancy cannot be executed in the row block unit, and the degree of freedom of redundancy tends to be limited.